The present invention relates generally to semiconductor device processing and, more particularly, to a method for determining cell body and biasing plate contact location for embedded dynamic random access memory (eDRAM) in silicon-on-insulator (SOI) substrates.
Dynamic random access memory, or DRAM, is a type of semiconductor memory in which the information is stored as data bits in capacitors on a metal-oxide-semiconductor (MOS) integrated circuit. Each bit is typically stored as an amount of electrical charge in a storage cell consisting of a capacitor and a transistor. Due to charge leakage, the capacitor discharges gradually and the memory cell can lose the information. Therefore, to preserve the information, the memory must be refreshed periodically. Despite this inconvenience, the DRAM is a very popular memory technology because of its high density and consequent low price.
Conventional semiconductor DRAM devices are formed in bulk semiconductive substrate material by implanting a well of either p-type or n-type material in a wafer of either type material. Gates and source/drain diffusions are then manufactured using commonly known processes. These can form devices known as metal-oxide-semiconductor field effect transistors, or MOSFETs. When a given chip uses both p-type and n-type semiconductors, it is known as a complementary metal oxide semiconductor (CMOS) chip. Each of these type devices must be electrically isolated from the others in order to avoid electrical shorting of the circuits. A relatively large amount of surface area is needed for the electrical isolation of the various FETs, which is undesirable in the current trend toward overall size reduction and greater integration. Additionally, parasitic paths and junction capacitance problems may be present because of the physical proximity of the source/drain diffusions to other FETs and to the bulk substrate. These problems more frequently arise when trying to scale circuitry down to the sizes necessary for greater circuit density.
Silicon-on-insulator (SOI) technology is one approach that has been increasingly used to alleviate these problems. However, SOI devices may suffer from problems such as self-heating, electrostatic discharge susceptibility, low breakdown voltage, and dynamic floating body effects, which in turn present problems for passgate devices and devices requiring tight threshold voltage control. The so-called “floating body effect” occurs when the body of the device is not connected to a fixed potential and, therefore, the device takes on a charge based on the history of the device. The floating body effect greatly affects device reliability.
Certain types of semiconductor memory are more susceptible to the floating body effect. For instance, in dynamic random access memory (DRAM) the information is stored in capacitors in an MOS circuit. Thus, in DRAM, the floating body effect is especially detrimental since it is critical that the associated transistor stays in an “off” condition to prevent charge leakage from the storage capacitor. As such, it is generally advantageous to form a DRAM array in bulk silicon regions, and advantageous to form other logic devices in an SOI region. In the case of an embedded DRAM (eDRAM) device, such as is found in the area of Application Specific Integrated Circuit (ASIC) technologies for example, the memory array region of the device is generally formed in proximity to the support regions of the device. As result, eDRAM devices have recently been formed within a designed bulk/SOI hybrid substrate, wherein the DRAM devices are formed in the bulk regions of the hybrid substrate and the support devices are formed in the SOI regions of the hybrid substrate.
For such configurations, one existing approach has been to pattern and create both bulk and SOI regions on the same wafer by processes such as separation by implantation of oxygen (SIMOX), for example. However, the additional lithography, patterning and implantation steps associated therewith increase the overall manufacturing costs of the device. Accordingly, it would be desirable to be able to form both support and area areas of an eDRAM device on a uniform substrate (such as an SOI substrate), while still retaining the benefits of a hybrid substrate in terms of device performance.